1. Field of the Invention
The present invention relates to a design pattern correction method of correcting a design pattern of a semiconductor integrated circuit. Moreover, the present invention relates to a mask pattern producing method of producing a mask pattern of a semiconductor integrated circuit.
2. Description of the Related Art
Recently, the technique of manufacturing semiconductor devices has remarkably advanced, and semiconductor devices having a minimum process dimension of 0.13 μm are mass-produced. The scale-down described above is realized by the great development of micro-pattern forming techniques such as mask process techniques, photolithography techniques and etching techniques.
In the large pattern size generation, an LSI pattern to be formed on a wafer is intactly used as a design pattern, and a mask pattern faithful to the design pattern is produced. The mask pattern is transferred onto the wafer using a projection optical system, thereby forming a pattern approximately equal to the design pattern on the wafer.
However, the scale-down of the pattern advances; for this reason, it is difficult to faithfully form a pattern in individual processes. As a result, a problem arises such that the final processed pattern shape is not provided as the design pattern.
In order to overcome the foregoing problem, so-called mask data processing is very important. More specifically, a mask pattern different from the design pattern is produced so that the final processed pattern dimensions become approximately equal to the design pattern.
The mask data processing includes the following processings. One is MDP processing of modifying the mask pattern using graphical operation and a design rule checker (D.R.C.). Another is optical proximity. correction (OPC) for correcting the optical proximity effect (OPE). The foregoing processings are made, and thereby, the mask pattern is properly corrected so that the final processed pattern dimensions are provided as desired dimensions.
In recent years, a k1 value (k1=W/(NA/λ)) becomes smaller and smaller in the lithography process with the scale-down of device patterns. (In the foregoing equation, W: design pattern dimension, λ: exposure wavelength of exposure system, and NA: numerical aperture of a lens used for the exposure system.) As a result, there is a tendency for the influence of the OPE to increase. For this reason, a very heavy load is given to the OPC.
In order to achieve high accuracy of the OPC, a model-based OPC is mainly employed. According to the model-based OPC, a proper correction value is calculated using a light intensity simulator capable of accurately predicting the OPE. A model-based OPC verification technique using lithography simulation is very important to verify a mask subjected to complicated model-based OPC.
For example, there have been proposed techniques of applying the model-based OPC verification technique to a single layer to detect a dangerous pattern having a small lithography margin (see U.S. Pat. No. 6,470,489 and U.S. Pat. No. 6,415,421). However, according to the foregoing techniques, sufficient detection accuracy is not obtained. In addition, development is still not made with respect to a technique of determining whether or not a sufficient lithography margin is secured between several layers.
Consequently, it is difficult to secure a sufficient processed shape in the conventional case. In addition, if a sufficient processed shape is secured, the problem arises such that the layout area increases; as a result, the chip size also increases.